1. Field of the Invention
The present invention relates to a device for generating a reference voltage, and more particularly to a reference voltage generating circuit for generating a reference voltage which is controllable with programmable codes.
2. Description of the Related Art
Generally, a reference voltage is used in a logic circuit as a threshold voltage for determining logic levels of data. As shown in FIG. 1, when a reference voltage Vref is used as the threshold voltage to determine levels of data, the data is determined to have a logic xe2x80x9clow levelxe2x80x9d if the data is lower than the reference voltage Vref and to have a logic xe2x80x9chigh levelxe2x80x9d if the data is higher than the reference voltage Vref.
FIG. 2 shows a system board 200 in which a reference voltage Vref is supplied to multiple chips. The reference voltage Vref is generated from a reference voltage generating circuit 202 and supplied to the respective chips 210, 212, 214, . . . n. In this case, the level of the reference voltage Vref may vary with the difference in physical distance between the reference voltage generating circuit 202 and the respective chips 210, 212, 214, . . . n. As shown in FIG. 2, the first chip 210 is positioned near the reference voltage generating circuit 202, so that a reference voltage supplied to the first chip 210 has level xe2x80x9cAxe2x80x9d which is substantially equal to the level of the reference voltage Vref generated from the reference voltage generating circuit 202. Since the second chip 212 is positioned relatively far from the reference voltage generating circuit 202, a reference voltage supplied to the second chip 212 has level xe2x80x9cBxe2x80x9d which is slightly lower than the level of the reference voltage Vref. Since the third chip 214 is positioned relatively farther from the reference voltage generating circuit 202 than the first and second chips 210, 212, a reference voltage supplied to the third chip 214 has level xe2x80x9cCxe2x80x9d and is even lower than the level of the reference voltage Vref.
In such an environment, the reference voltages supplied to the respective chips 210, 212, 214 are different from each other, and the threshold voltage for determining logic levels of data varies in different chips. As a result, in the third chip 214 receiving the reference voltage with level xe2x80x9cCxe2x80x9d, there is a problem in that data is determined to be logic xe2x80x9chighxe2x80x9d in regions xe2x80x9cE1xe2x80x9d and xe2x80x9cE2xe2x80x9d, which would have been determined as logic xe2x80x9clowxe2x80x9d.
As speed of data interface between the chips is increased, swing width of external signals as well as data is needed to be smaller. Thus, in high speed data interface circumstances, noise of a reference voltage supplied from an external may affect the determination of logic levels (e.g., VIL, VIH) of input signals.
Accordingly, a need exists for a system which provides a reference voltage having a stable level to the chips where the reference voltage is used for determining logic levels of input data.
It is an object of the present invention to provide a reference voltage generating circuit for generating a programmable reference voltage in response to an external code.
Another object of the present invention is to provide a method of arranging the reference voltage generating circuit.
To accomplish the above and other objects of the present invention, a reference voltage generating circuit comprises a binary-to-thermometer for converting binary codes into thermometer codes; an internal reference voltage generator for generating an internal reference voltage in response to the thermometer codes from the binary-to-thermometer, wherein the internal reference voltage generator changes a level of the internal reference voltage in response to the thermometer codes; a selector for selecting the internal reference voltage or an external reference voltage in response to a reference voltage select signal; and a voltage regulator for regulating a reference voltage selected by the selector.
The binary-to-thermometer comprises thermometer code generators for generating the thermometer codes in response to the binary codes. The thermometer code generators each include a logic gate for selectively inputting the binary codes, transmission gates for transmitting an output of the logic gate to generate a thermometer code in response to a selected signal (e.g., the MSB) of the binary codes, and transistors for resetting the thermometer code in response to the selected signal (e.g., the MSB) of the binary codes.
The internal reference voltage generator includes a reference voltage bias part having a diode type first transistor connected between a power source voltage and the internal reference voltage and a diode type second transistor connected between the internal reference voltage and ground voltage, and a reference voltage coding part for increasing or decreasing the internal reference voltage in response to the thermometer codes.
The reference voltage coding part includes voltage-up controllers connected between the power source voltage and the internal reference voltage, for increasing the internal reference voltage in response to the thermometer codes, and voltage-down controllers connected between the internal reference voltage and the ground voltage, for decreasing the internal reference voltage in response the thermometer codes.
The voltage-up controllers each include inverter type first and second transistors connected between the power source voltage and the internal reference voltage and controlled by the thermometer codes, and a third transistor connected between the power source voltage and the internal reference voltage, for increasing the internal reference voltage in response to outputs of the first and second transistors. The voltage-down controllers each include inverter type fourth and fifth transistors connected between the internal reference voltage and the ground voltage and controlled by the thermometer codes, and a sixth transistor connected between the internal reference voltage and the ground voltage for decreasing the internal reference voltage in response to outputs of the fourth and fifth transistors.
To accomplish another object, a method of arranging reference voltage generating circuits in a chip, comprises the steps of arranging in the chip devices sharing a reference voltage generated from the reference voltage generating circuits; and arranging the reference voltage generating circuit at the end sides of the chip, wherein the devices are connected in common with the reference voltage generating circuits. The step of arranging the reference voltage generating circuits includes arranging one reference voltage generating circuit at one end side of the chip; and arranging the other reference voltage generating circuit at the other end side of the chip, wherein the two end sides are opposite to each other.
According to the present invention as described above, there is an advantage that a reference voltage is controlled using programmable codes. In addition, reference voltage generating circuits may be disposed at predetermined positions (e.g., the end sides opposite to each other) of a chip having devices receiving and sharing a reference voltage, thereby reducing the chip size and to prevent occurrence of errors due to a mismatch between the reference voltage generating circuits.